PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 168

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MODED
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data.
STI ... Start Timer 1
The ISAC-SX timer 1 is started when STI is set to one. The timer is stopped by writing
to the TIMR1 register.
Note: Timer 2 is controlled by the TIMR2 register only.
XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMD1.XFBS) to the XFIFOD, the
microcontroller initiates the transmission of a transparent frame by setting this bit to ’1’.
The opening flag is automatically added to the message by the ISAC-SX (except in the
extended transparent mode where no flags are used).
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOD completes the corresponding frame. The ISAC-SX terminates the transmission
by appending the CRC (if EXMD1.XCRC=0) and the closing flag sequence to the data
(except in the extended transparent mode where no such framing is used).
XRES ... Transmitter Reset
The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOD and the
4.1.7
Value after reset: C0
Data Sheet
appropriate Transmit Command (XTF) has to be written to the CMDRD register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAD).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
7
MDS2 MDS1 MDS0
MODED - Mode Register
H
0
168
RAC
DIM2
Detailed Register Description
DIM1
0
DIM0
RD/WR (22)
PEB 3086
2003-01-30
ISAC-SX