PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 64

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.3.10
The layer-1 part of the ISAC-SX can be enabled/disabled by configuration (see
Figure
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the ISAC-SX does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The HDLC controller can still operate via IOM-2. The
DCL and FSC pins become input.
Figure 32
3.3.11
The ISAC-SX provides test and diagnostic functions for the S/T interface:
Note: For more details please refer to the application note “Test Function of new
– The internal local loop (internal Loop A) is activated by a C/I command ARL or by
Data Sheet
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
is disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 input B- and D-channels are looped back to the output B- and D-
channels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
affected.
S-Transceiver family”
32) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX.
Test Functions
Transceiver Enable/Disable
Disabling of S/T Transmitter
TR_CONF0.DIS_TR
64
TR_CONF2.DIS_TX
Description of Functional Blocks
’1’
’0’
PEB 3086
2003-01-30
ISAC-SX