PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 41

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PEB3086HV14XP

Manufacturer Part Number
PEB3086HV14XP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB3086HV14XP

Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
3.2.4
Figure 9
.
Figure 9
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Data Sheet
C/I Code Change
(Exchange Awake)
EAW
(Subscriber Awake)
Watchdog
Software Reset
Register (SRES)
Reset
Functional
Block
Internal Reset of all Registers
shows the organization of the reset generation of the device.
Reset Generation
Reset MODE1 Register
D, C/I-channel (00
Transceiver (30
IOM-2 (40
MON-channel (5C
General Config (60
B-channel (70
Reset Generation
125µs £ t £ 250µs
125µs £ t £ 250µs
125µs £ t £ 250µs
125µs £ t £ 250µs
H
-5B
H
H
-7F
)
H
-3F
H
H
H
H
-2F
)
-5F
H
-6F
)
H
H
H
)
)
)
³ 1
'0'
'1'
RSS1
'1x'
'00'
RSS2,1
41
Table
³ 1
Description of Functional Blocks
6.
' 01 '
(reserved)
'01'
RSS2,1
³ 1
Pin
RES
Pin
RSTO
3086_21
PEB 3086
2003-01-30
ISAC-SX

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