FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 76

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.1.5
76
Figure 5-3. NMI# Generation Logic
Note: If NMIs are enabled, and parity error checking on PCI is also enabled, then parity errors will cause
Parity Error Detection
The ICH4 can detect and report different parity errors in the system. The ICH4 can be programmed
to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The
conceptual logic diagram in
with their respective enable bits, status bits, and the results.
an NMI. Some operating systems will not attempt to recover from this NMI, since it considers the
detection of a PCI error to be a catastrophic event.
IOCHK From SERIRQ Logic
D30:F0 PDSTS
D30:F0 SECSTS
during LPC or Legacy DMA
[PCI_SERR_EN]
PCI Parity Error detected
during AC'97, IDE or USB
PCI Parity Error detected
[Parity Error Response
D30:F0 BRIDGE_CNT
[SSE]
[Parity Error Response]
NMI_SC
[SSE]
Master Cycle
Hub Interface Parity
Master Cycle
[IOCHK_NMI_EN]
D30:F0 CMD
D31:F0 PCICMD
Error Detected
Enable]
NMI_SC
[PER]
OR
Figure 5-3
AND
AND
AND
[HUBNMI_STS]
AND
TCO1_STS
[NMI_NOW]
TCO1_CNT
AND
details all the parity errors that the ICH4 can detect, along
D30:F0 SECSTS
[SERR#_NMI_STS]
[DPD]
D31:F0 PCISTA
D30:F0 PD_STS
[IOCHK_NMI_STS]
NMI_SC
[DPED]
[DPD]
NMI_SC
OR
OR
[NMI_EN]
NMI_EN
Intel
OR
®
82801DBM ICH4-M Datasheet
AND
To NMI#
Output
Gating
Logic
and