FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 226

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.18.1.1
226
Table 5-78. Quick Protocol
Table 5-79. Send / Receive Byte Protocol without PEC
Using the SMB Host Controller to send commands to the ICH4's SMB slave port is supported. The
ICH4 supports slave functionality, including the Host Notify protocol, on the SMLink pins.
Therefore, to be fully compliant with the SMBus 2.0 specification (which requires the Host Notify
protocol), the SMLink and SMBus signals should be tied together externally.
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the
progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the
command completes successfully, the INTR bit will be set in the Host Status Register. If the device
does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If
software sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC
byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when
performing the Quick Command. Software must force the I2C_EN bit to 0 when running this
command.The format of the protocol is shown in
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is
stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this
command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data transfer. The
format of the protocol is shown in
11–18
2–8
Bit
10
19
20
1
9
2–8
Bit
10
11
1
9
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Stop
Send Byte Protocol
Description
Start Condition
Slave Address - 7 bits
Read / Write Direction
Acknowledge from slave
Stop
Description
Table
5-79. and
Table
Table 5-80
11–18
2–8
Bit
19
20
10
1
9
5-78.
Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data byte from slave
NOT Acknowledge
Stop
Intel
Receive Byte Protocol
®
82801DBM ICH4-M Datasheet
Description