FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 296

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.16
296
SECSTS—Secondary Status Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
10:9
4:0
Bit
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = This bit is cleared by software writing a 1.
1 = ICH4 detected a parity error on the PCI bus.
Received System Error (SSE) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = SERR# assertion is received on PCI.
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Hub interface to PCI cycle is master-aborted on PCI.
Received Target Abort (RTA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the
Signaled Target Abort (STA) —RO. The ICH4 does not generate target aborts.
DEVSEL# Timing Status (DEV_STS) — RO.
01h = Medium timing.
Master Data Parity Error Detected (MDPD) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = The ICH4 sets this bit when all of the following three conditions are met:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1 to indicate that the PCI to hub interface
target logic is capable of receiving fast back-to-back cycles.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Reserved
• The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set
• USB, AC ’97 or IDE is a Master
• PERR# asserts during a write cycle OR a parity error is detected internally during a read cycle
hub interface, this event should also set the Signaled Target Abort in the Primary Status
Register in this device, and the ICH4 must send the “target abort” status back to the hub
interface.
1E–1Fh
0280h
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/WC
16 bits