FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 427

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

11.2
Intel
®
Table 11-2. USB I/O Registers
82801DBM ICH4-M Datasheet
USB I/O Registers
Some of the read/write register bits which deal with changing the state of the USB hub ports
function such that on read back they reflect the current state of the port, and not necessarily the
state of the last write to the register. This allows the software to poll the state of the port and wait
until it is in the proper state before proceeding. A Host Controller Reset, Global Reset, or Port
Reset will immediately terminate a transfer on the affected ports and disable the port. This affects
the USBCMD register, bit [4] and the PORTSC registers, bits [12, 6, 2]. See individual bit
descriptions for more detail.
NOTES:
1. These registers are Word writable only. Byte writes to these registers have unpredictable effects.
1
0
0D–0Fh
08–0Bh
00–01h
02–03h
04–05h
06–07h
10–11h
12–13h
14–17h
Offset
0Ch
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
FRBASEADD
Mnemonic
PORTSC0
PORTSC1
USBINTR
SOFMOD
USBCMD
USBSTS
FRNUM
USB Command
USB Status
USB Interrupt Enable
USB Frame Number
USB Frame List Base Address
USB Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
Reserved
Register
USB UHCI Controllers Registers
Undefined
Default
0000h
0020h
0000h
0000h
0080h
0080h
40h
0
0
R/WC, R/W,
R/WC, R/W,
R/W
R/WC
RO
RO
Type
R/W
R/W
R/W
R/W
RO
RO
(1)
(1)
(1)
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