FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 580

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Testability
19.2
19.3
19.3.1
580
Figure 19-2. Example XOR Chain Circuitry
Table 19-2. XOR Test Pattern Example
Tri-State Mode
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the XOR
chain outputs.
XOR Chain Mode
In the ICH4, provisions for Automated Test Equipment (ATE) board level testing are implemented
with XOR chains. The ICH4 signals are grouped into four independent XOR chains which are
enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within
that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain
(except for the XOR chain’s output) functions as an input. All output and bi-directional buffers for
pins not in the selected XOR chain are tri-stated.
circuitry.
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity
(e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in
In this example, Vector 1 applies all 0s to the chain inputs. The outputs being non-inverting, will
consistently produce a 1 at the XOR output on a good board. One short to VCC (or open floating to
VCC) will result in a 0 at the chain output, signaling a defect.
Vector
Vcc
Input
Pin 1
1
2
3
4
5
6
7
Input
Pin 1
0
1
1
1
1
1
1
Input
Pin 2
Input
Pin 2
0
0
1
1
1
1
1
Input
Pin 3
Input
Pin 3
0
0
0
1
1
1
1
Input
Pin 4
Figure 19-2
Input
Pin 4
0
0
0
0
1
1
1
Input
Pin 5
is a schematic example of XOR chain
Intel
Input
Pin 5
0
0
0
0
0
1
1
®
82801DBM ICH4-M Datasheet
Input
Pin 6
Input
Pin 6
0
0
0
0
0
0
1
Table
Output
XOR
1
0
1
0
1
0
1
Output
Chain
XOR
19-2.