FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 450

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FW82801DBM S L6DN

Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DBM S L6DN

Lead Free Status / RoHS Status
Not Compliant
EHCI Controller Registers (D29:F7)
450
Bit
5
4
3
2
1
0
SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit is a 1, the host controller will
SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error is a 1, the host controller will
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit is a 1, the host controller
SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit is a 1, the host controller
SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit is a 1, the host controller will issue an
SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit is a 1, the host controller will
issue an SMI immediately.
issue an SMI.
will issue an SMI.
will issue an SMI.
SMI immediately.
issue an SMI immediately.
Description
Intel
®
82801DBM ICH4-M Datasheet

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