FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 430

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

USB UHCI Controllers Registers
430
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts. When a valid TD
is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS
register (bit 5) is set.
The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed.
When the last active TD in a frame has been executed, the Host Controller waits until the next SOF
is sent and then fetches the first TD of the next frame before halting.
This HCHalted bit can also be used outside of Software Debug mode to indicate when the Host
Controller has detected the Run/Stop bit and has completed the current transaction. Outside of the
Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the
Run/Stop bit is set the Host Controller starts over again from the frame list location pointed to by
the Frame List Index (see FRNUM Register description) rather than continuing where it stopped.
10. HCD sets Run/Stop bit to 1 to resume normal schedule execution.
3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame
4. HCD sets Run/Stop bit to 1.
5. Host Controller executes next active TD, sets Run/Stop bit to 0, and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end
8. HCD ends Software Debug mode by setting SWDBG bit to 0.
9. HCD sets up normal command list and Frame List table.
List Single Step Loop.
(HCHalted=1).
Software Debug mode.
Intel
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82801DBM ICH4-M Datasheet