FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 399

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.10.5
9.10.6
Intel
®
82801DBM ICH4-M Datasheet
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address:
Default Value:
Lockable:
13:11, 8
10:9, 6
31:14,
7, 5:0
31:0
Bit
Bit
Reserved
GP_INV[n]
SMI# or SCI. Note that in the S0 or S1-M state, the input signal must be active for at least 2 PCI
clocks to ensure detection by the ICH4. In the S3, S4 or S5 states the input signal must be active
for at least 2 RTC clocks to ensure detection. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in the
Resume well, and will be reset to their default values by RSMRST# or a write to the CF9h
register.
0 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
1 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
GP_INV[n]
SMI# or SCI. Note that in the S0 or S1-M state, the input signal must be active for at least 2 PCI
clocks to ensure detection by the ICH4. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an output. These bits correspond to GPIO that are in the
Core well, and will be reset to their default values by PCIRST#.
0 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
1 = The corresponding GPI_STS bit will be set when the ICH4 detects the state of the input pin
GPIO_USE_SEL2[43:32]
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured
as their native function rather than as a GPIO. After just a PCIRST#, the GPIO in the core well are
configured as their native function.
1. The following bits are not implemented because there is no corresponding GPIO: 31:12
2. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have
no effect.
to be high.
to be low.
to be high.
to be low.
GPIOBASE +2Ch
00000000h
No
GPIOBASE +30h
00000FFFh
No
—
—
R/W. These bits are used to allow both active-low and active-high inputs to cause
R/W. These bits are used to allow both active-low and active-high inputs to cause
—
R/W. Each bit in this register enables the corresponding GPIO (if it
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
See bit description
R/W
32-bit
Core
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