FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 50

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.7
2.8
50
Table 2-7. LPC Interface Signals
Table 2-8. Interrupt Signals
LPC Interface
Interrupt Interface
LAD[3:0] /
FWH[3:0]
LFRAME# /
FWH[4]
LDRQ[1:0]#
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]# /
GPIO[5:2]
IRQ[14:15]
APICCLK
APICD[1:0]
Name
Name
Type
I/O
O
I
Type
I/OD
I/OD
I/OD
I/O
I
I
LPC Multiplexed Command, Address, Data: For the LAD[3:0] signals, internal pull-
ups are provided.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or
bus master access. These signals are typically connected to an external Super I/O
device. An internal pull-up resistor is provided on these signals.
Serial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt
Steering section. Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the legacy interrupts.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt
Steering section. Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21,
PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the legacy interrupts. If
not needed for interrupts, these signals can be used as GPIO.
Interrupt Request 14:15: These interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the Primary controller and
IRQ15 is used by the drives connected to the Secondary controller.
APIC Clock: This clock operates up to 33.33 MHz.
APIC Data: These bi-directional open drain signals are used to send and
receive data over the APIC bus. As inputs the data is valid on the rising edge of
APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
Description
Description
Intel
®
82801DBM ICH4-M Datasheet