FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 346

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.4.10
346
ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address:
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating
point error interrupt, IRQ13, cannot be programmed for level mode.
Bit
7
6
5
4
3
2
1
0
IRQ15 ECL — R/W.
0 = Edge.
1 = Level.
IRQ14 ECL — R/W.
0 = Edge.
1 = Level.
Reserved. Must be 0.
IRQ12 ECL — R/W.
0 = Edge.
1 = Level.
IRQ11 ECL — R/W.
0 = Edge.
1 = Level.
IRQ10 ECL — R/W.
0 = Edge.
1 = Level.
IRQ9 ECL — R/W.
0 = Edge.
1 = Level.
Reserved. Must be 0.
4D1h
00h
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits