FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 492

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
14.1.4
492
PCISTS—PCI Device Status Register (Audio—D31:F5)
Offset:
Default Value
Lockable:
PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details on each
bit.
10:9
Bit
3:0
15
14
13
12
11
8
7
6
5
4
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort.
Reserved. Will always read as 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the ICH4's DEVSEL# timing
when performing a positive decode.
01b = Medium timing.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the ICH4 as a
target is capable of fast back-to-back transactions.
User Definable Features (UDF) — RO. Not implemented. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CLIST) — RO. Indicates that the controller contains a capabilities pointer list. The
first item is pointed to by looking at configuration offset 34h.
Reserved.
0280h
06
No
–
07h
Description
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
R/WC, RO
16 bits
Core