FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 171

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 5-49. Alert on LAN* Message Data
82801DBM ICH4-M Datasheet
Note: Section 5.13.2 describes the “Processor Missing Event Status” and how an Alert Message can be
Once the system transitions to the non-S0 state, it may send a single alert with an incremental
SEQUENCE number.
sent via LAN. This feature is meant to function when a processor is installed in the socket (but is
non-functional) and was not intended to alert when the processor was not installed. When the
processor is not installed, VRMPWRGD is programmed not to assert which prevents TCO timer
operation. It is this timer that is used to set the SECOND_TO_STS bit in TCO2_STS
(TCOBase+60h), used for the alert.
To enable this messaging without a processor installed in the socket, external logic, monitoring
processor socket signal SKTOCC#, should drive VID:4] low which will enable the VRM to drive
its CPUPWRGD signal, which in turn will allow the CPU Dead Alert to function under this empty
socket condition.
Table 5-49
Cover Tamper Status
Temp Event Status
Processor Missing Event Status
TCO Timer Event Status
Software Event Status
Unprogrammed FWH Event Status
GPIO Status
2. WARNING: It is important that the BIOS clears the SECOND_TO_STS bit, as the alerts will
3. A system that has locked up and can not be restarted with power button press is assumed to
4. A spurious alert could occur in the following sequence:
5. An inaccurate alert message can be generated in the following scenario.
interfere with the LAN device driver from working properly. The alerts reset part of the D110
and would prevent an operating system’s device driver from sending or receiving some
messages.
have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond
ICH4’s recovery mechanisms.
— The processor has initiated an alert using the SEND_NOW bit.
— During the alert, the THRM#, INTRUDER# or GPI[11] changes state.
— The system then goes to a non-S0 state.
— The system successfully boots after a second watchdog Timeout occurs.
— PWROK goes low (typically, due to a reset button press) or a power button override
— An alert message indicating that the processor is missing or locked up is generated with a
occurs (before the SECOND_TO_STS bit is cleared).
new sequence number.
shows the data included in the Alert on LAN messages.
Field
1 = This bit will be set if the intruder detect bit is set (INTRD_DET).
1 = This bit will be set if the ICH4 THERM# input signal is asserted.
1 = This bit is set when the TCO timer expires.
1 = This bit is set when software writes a 1 to the SEND_NOW bit.
1 = First BIOS fetch returned a value of FFh, indicating that the FWH has
not yet been programmed (still erased).
1 = This bit is set when GPIO[11] signal is high.
0 = This bit is cleared when GPIO[11] signal is low.
An event message is triggered on an transition of GPIO[11].
1 = This bit will be set if the processor failed to fetch the first instruction.
Comment
Functional Description
171