FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 440

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
12.1.4
12.1.5
440
PCISTS—PCI Device Status Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
REVID—Revision ID Register (USB EHCI—D29:F7)
Offset Address:
Default Value:
10:9
7:0
3:0
Bit
Bit
15
14
13
12
11
8
7
6
5
4
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = ICH4 signaled SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be 1
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = USB EHCI, as a master, received a master abort status on a memory access. This is treated as
Received Target Abort (RTA) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = USB EHCI, as a master, received a target abort status on a memory access. This is treated as
Signaled Target Abort (STA) — RO. Hardwired to 0. This bit is used to indicate when the USB EHCI
function responds to a cycle with a target abort. There is no reason for this to happen; thus, this bit is
hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion.
Master Data Parity Error Detected (DPED) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = ICH4 detected a data parity error on a USB EHCI read completion packet on the internal
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Capabilities List (CAP_LIST) — RO. This bit is hardwired to 1 indicating the presence of a valid
capabilities pointer at offset 34h.
Reserved.
for this bit to be set.
a Host Error and halts the DMA engines. This event can optionally generate an SERR# by
setting the SERR# Enable bit
a Host Error and halts the DMA engines. This event can optionally generate an SERR# by
setting the SERR# Enable bit
interface to the USB EHCI host controller (due to an equivalent data parity error on hub
interface), and bit 6 of the Command register is set to 1.
0290h
08h
06
See Bit Description
–
07h
.
.
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
R/WC, RO
16 bits
®
82801DBM ICH4-M Datasheet
RO
8 bits