WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 89

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 56. Transmit Control Register - Address 30, Hex 1E
Table 56
30.15:13
30.12
30.11:10
30.9:0
1. Values are approximations and may vary outside indicated values based upon implementation loading
2. R/W = Read/Write
3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L.
Bit
conditions. Not guaranteed.
lists transmit control bits.
Reserved
Transmit Low Power
Port Rise Time Control
Reserved
Name
Intel
1
Write as ‘0’. Ignore on Read.
Transmit Low Power
0 = Normal transmission.
1 = Forces the transmitter into low power mode.
Port Rise Time Control
00 = 3.0 ns (Default)
01 = 3.4 ns
10 = 3.9 ns
11 = 4.4 ns
Ignore on Read.
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Also forces a zero-differential transmission.
Description
Type
R/W
R/W
R/W
R/W
2
0000000
Default
000
000
00
0
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