WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 3

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Introduction to This Document ......................................................................................... 10
1.1
1.2
Block Diagram for Intel
Pin Assignments for Intel
Signal Descriptions for Intel
Functional Description...................................................................................................... 21
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Document Overview ............................................................................................10
Related Documents............................................................................................. 10
Device Overview .................................................................................................22
5.1.1
5.1.2
Network Media / Protocol Support.......................................................................23
5.2.1
5.2.2
5.2.3
Operating Requirements .....................................................................................28
5.3.1
5.3.2
Initialization.......................................................................................................... 29
5.4.1
5.4.2
5.4.3
5.4.4
Establishing Link .................................................................................................34
5.5.1
5.5.2
MII Operation....................................................................................................... 36
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
100 Mbps Operation ............................................................................................41
5.7.1
5.7.2
5.7.3
10 Mbps Operation.............................................................................................. 50
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Comprehensive Functionality ................................................................. 22
Optimal Signal Processing Architecture ................................................. 22
10/100 Network Interface .......................................................................23
MII Data Interface ................................................................................... 25
Configuration Management Interface ..................................................... 25
Power Requirements ..............................................................................28
Clock Requirements ............................................................................... 28
MDIO Control Mode and Hardware Control Mode .................................31
Reduced-Power Modes .......................................................................... 31
Reset for Intel
Hardware Configuration Settings ...........................................................33
Auto-Negotiation.....................................................................................34
Parallel Detection ................................................................................... 35
MII Clocks............................................................................................... 37
Transmit Enable .....................................................................................38
Receive Data Valid ................................................................................. 38
Carrier Sense ......................................................................................... 39
Error Signals........................................................................................... 39
Collision .................................................................................................. 39
Loopback................................................................................................ 40
100BASE-X Network Operations ...........................................................41
Collision Indication ................................................................................. 44
100BASE-X Protocol Sublayer Operations ............................................ 45
10BASE-T Preamble Handling ............................................................... 50
10BASE-T Carrier Sense .......................................................................50
10BASE-T Dribble Bits ........................................................................... 50
10BASE-T Link Integrity Test ................................................................. 51
Link Failure ............................................................................................. 51
®
LXT972M Transceiver............................................................... 11
®
LXT972M Transceiver ...........................................................12
Intel
®
LXT972M Transceiver ....................................................... 15
®
®
LXT972M Transceiver................................................... 31
LXT972M Single-Port 10/100 Mbps PHY Transceiver
3