WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 55

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

5.10
5.10.1
5.10.2
5.10.3
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 16. Valid JTAG Instructions
Note: For the related BSDL file, contact your local sales office or access the Intel website
Boundary Scan (JTAG 1149.1) Functions
The LXT972M Transceiver includes a IEEE 1149.1 boundary scan test port for board level testing.
All digital input, output, and input/output pins are accessible.
(www.intel.com).
Boundary Scan Interface
The boundary scan interface consists of five pins (TMS, TDI, TDO, TRST_L, and TCK). It
includes a state machine, data register array, and instruction register. The TMS and TDI pins are
pulled up internally. TCK is pulled down internally. TDO does not have an internal pull-up or pull-
down.
State Machine
The TAP controller is a state machine, with 16 states driven by the TCK and TMS pins. Upon reset,
the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
high for five TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction.
Table 16
EXTEST
IDCODE
SAMPLE
HIGHZ
CLAMP
BYPASS
Name
lists valid JTAG instructions for the LXT972M Transceiver.
1111 1111 1110 1000
1111 1111 1111 1110
1111 1111 1111 1000
1111 1111 1100 1111
1111 1111 1110 1111
1111 1111 1111 1111
Code
Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
External Test
ID Code Inspection
Sample Boundary
Force Float
Control Boundary to 1/0
Bypass Scan
Description
Test
Normal
Normal
Normal
Test
Normal
Mode
BSR
ID REG
BSR
Bypass
Bypass
Bypass
Data Register
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