WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 84

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
84
Table 51. Configuration Register - Address 16, Hex 10
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Table 51
16.4:3
16.15
16.14
16.13
16.12
16.11
16.10
1. R/W = Read /Write
16.9
16.8
16.7
16.6
16.5
16.2
16.1
16.0
Bit
lists configuration bits.
Reserved
Force Link Pass
Transmit Disable
Bypass Scrambler
(100BASE-TX)
Reserved
Jabber
(10BASE-T)
SQE
(10BASE-T)
TP Loopback
(10BASE-T)
CRS Select
(10BASE-T)
Reserved
PRE_EN
Reserved
Reserved
Alternate NP
feature
Reserved
Name
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Force Link pass
0 = Normal operation
1 = Disable Twisted Pair transmitter
0 = Normal operation
1 = Bypass Scrambler and Descrambler
Write as ‘0’. Ignore on Read.
0 = Normal operation
1 = Disable Jabber Correction
0 = Disable Heart Beat
1 = Enable Heart Beat
0 = Normal operation
1 = Disable TP loopback during half-duplex
0 = Normal Operation
1 = CRS deassert extends to RX_DV deassert
Write as ‘0’. Ignore on Read.
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
NOTE: Preamble is always enabled in 100 Mbps
Write as ‘0’. Ignore on Read.
Write as ‘0’. Ignore on Read.
0 = Disable alternate auto negotiate next page
1 = Enable alternate auto negotiate next page
This bit enables or disables the register bit 6.5
capability.
Write as ‘0’. Ignore on Read.
operation
CRS is asserted.
feature.
feature.
operation.
Description
Document Number: 302875-005
Revision Date: 27-Oct-2005
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Datasheet
Default
00
0
0
0
0
0
0
0
0
1
0
0
0
0
0