WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 40

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WJLXT972MLC.A4 S L7U9

Manufacturer Part Number
WJLXT972MLC.A4 S L7U9
Description
Manufacturer
Intel
Datasheet

Specifications of WJLXT972MLC.A4 S L7U9

Lead Free Status / RoHS Status
Compliant
Intel
5.6.7
5.6.7.1
40
Figure 10. Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Loopback
The LXT972M Transceiver provides the following loopback functions:
Figure 10
Operational Loopback
Section 5.6.7.1, “Operational Loopback”
Section 5.6.7.2, “Internal Digital Loopback (Test Loopback)”
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0.
Data that the MAC (TXData) transmits loops back on the receive side of the MII (RXData).
Operational loopback is not provided for 100 Mbps links, full-duplex links, or when Register
16.8 = 1.
®
Intel® LXT972M Transceiver
LXT972M Transceiver Loopback Paths
shows LXT972M Transceiver loopback paths.
MII
Loopback
Operational
Loopback
10T
Digital
Block
Test Loopback
Loopback
100X
Analog
Block
Document Number: 302875-005
Revision Date: 27-Oct-2005
B3485-01
Driver
TX
Datasheet

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