WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 51

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

5.8.4
5.8.5
5.8.6
5.8.7
5.8.8
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT972M Transceiver always transmits link pulses.
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being
received. If this condition occurs, the LXT972M Transceiver returns to the auto-negotiation phase
if auto-negotiation is enabled. If the Link Integrity Test function is disabled by setting
Configuration Register bit 16.14 to ‘1’, the LXT972M Transceiver transmits packets, regardless of
link status.
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972M
Transceiver. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the
LXT972M Transceiver asserts its COL output for 5 to 15 bit times (BT) after each packet.
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT972M Transceiver disables the transmit and
loopback functions. For jabber timing parameters, see
10BASE-T Jabber and Unjabber Timing” on page
The LXT972M Transceiver automatically exits jabber mode after the unjabber time has expired.
This function can be disabled by setting Register bit 16.10 = 1.
10BASE-T Polarity Correction
The LXT972M Transceiver automatically detects and corrects for the condition in which the
receive signal (TPIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses - or
four inverted end-of-frame (EOF) markers - are received consecutively. If link pulses or data are
not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a
non-inverted state. When polarity reversal is detected in 10BASE-T operation, register 17.5 is set
to 1. (For details, see bit 17.5 in
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If the Link Integrity Test function is enabled (the normal configuration), the LXT972M
Transceiver monitors the connection for link pulses. Once link pulses are detected, data
transmission is enabled and remains enabled as long as either the link pulses or data
transmission continue. If the link pulses stop, the data transmission is disabled.
If the Link Integrity Test function is disabled (which can be done by setting Configuration
Register bit 16.14 to ‘1’), the LXT972M Transceiver transmits to the connection regardless of
detected link pulses.
Intel
Table 52, “Status Register #2 - Address 17, Hex 11” on page
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
69.
Figure 26, “Intel® LXT972M Transceiver
85.)
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