WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 36

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
5.6
36
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
MII Operation
This section includes the following topics:
The LXT972M Transceiver implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT972M Transceiver (TXD), and for passing data received from the line (RXD) to the MAC.
Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
The following signals are used to transmit data from the MAC:
The LXT972M Transceiver supplies both clock signals as well as separate outputs for carrier sense
and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
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Section 5.6.1, “MII Clocks”
Section 5.6.2, “Transmit Enable”
Section 5.6.3, “Receive Data Valid”
Section 5.6.4, “Carrier Sense”
Section 5.6.5, “Error Signals”
Section 5.6.6, “Collision”
Section 5.6.7, “Loopback”
COL
CRS
RX_CLK
RX_DV
RX_ER
RXD[3:0]
TX_CLK
TX_EN
TXD[3:0]
Document Number: 302875-005
Revision Date: 27-Oct-2005
Datasheet