WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 74

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
74
Figure 33. Intel
Table 39. Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
RESET_L pulse width
RESET_L recovery delay
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
testing.
performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300 μ s before accessing the MDIO port.
®
®
LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
LXT972M Transceiver RESET_L Pulse Width and Recovery Timing
Parameter
MDIO, and
RESET_L
so on
2
Symbol
t1
t2
Min
10
–
Typ
–
1
Max
300
–
t1
Units
ns
μ s
Document Number: 302875-005
t2
B3495-01
Revision Date: 27-Oct-2005
Test Conditions
Datasheet
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