WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 65

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

7.2
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 22. Intel
Table 30. Intel
Timing Diagrams
RXD[3:0], RX_DV, RX_ER
RX_CLK High
RXD[3:0], RX_DV, RX_ER hold
from RX_CLK High
CRS asserted to RXD[3:0], RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
3. RX_ER is not shown in the figure.
testing.
rate. 100BASE-T bit time = 10
®
®
LXT972M Transceiver 100BASE-TX Receive Timing Parameters
LXT972M Transceiver 100BASE-TX Receive Timing
Note: Timing diagram depicts 4B mode.
RXD[3:0]
RX_CLK
RX_DV
Parameter
CRS
COL
TPI
0 ns
3
setup to
Intel
-8
s or 10 ns.
®
t6
LXT972M Single-Port 10/100 Mbps PHY Transceiver
t4
Sym
t1
t2
t3
t4
t5
t6
t7
Min
10
10
12
10
16
17
3
t3
250 ns
Typ
–
–
–
–
–
–
–
1
Max
t5
16
17
22
20
t7
–
–
5
t1
t2
Units
B3492-03
BT
BT
BT
BT
BT
ns
ns
2
Test Conditions
–
–
–
–
–
–
–
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