WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 16

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
16
Table 4.
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Table 4
Intel
LQFP
Pin#
47
46
45
44
43
42
33
34
35
36
37
41
40
48
1
®
LXT972M Transceiver MII Data Interface Signal Descriptions
lists signal descriptions of the LXT972M Transceiver MII data interface pins.
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
RX_CLK
COL
CRS
Symbol
Type
O
O
O
O
O
O
O
I
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
Receive Data.
RXD is a group of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
Receive Data Valid.
The LXT972M Transceiver asserts this signal when it drives valid
data on RXD.
This output is synchronous to RX_CLK.
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see
“Functional
Collision Detected.
The LXT972M Transceiver asserts this output when a collision is
detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex
operation.
Carrier Sense.
During half-duplex operation (Register bit 0.8 = 0), the LXT972M
Transceiver asserts this output when either transmitting or receiving
data packets.
During full-duplex operation (Register bit 0.8 = 1), CRS is asserted
only during receive.
CRS assertion is asynchronous with respect to RX_CLK. CRS is
de-asserted on loss of carrier, synchronous to RX_CLK.
Description”.
“Clock Requirements” on page 28
Signal Description
Document Number: 302875-005
in
Chapter 5.0,
Revision Date: 27-Oct-2005
Datasheet