WJLXT972MLC.A4 S L7U9 Intel, WJLXT972MLC.A4 S L7U9 Datasheet - Page 42

• Manufacturer Part Number: WJLXT972MLC.A4 S L7U9
• Manufacturer: Intel

Specifications of WJLXT972MLC.A4 S L7U9

• Lead Free Status / RoHS Status: Compliant

Intel
42
Figure 12. 100BASE-TX Data Path
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver
As shown in
transmits the data to the network using MLT-3 line code. MLT-3 signals received from the network
are de-scrambled, decoded, and sent across the MII to the MAC.
Standard Data Flow
Scrambler Bypass Data Flow
D0
D1
D2
D3
S0
S1
S2
S3
S4
Parallel
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
to
to
to
to
Figure 12,
D0 D1 D2 D3
in 100BASE-TX mode, the LXT972M Transceiver scrambles and
4B/5B
S0 S1 S2 S3 S4
S0 S1 S2 S3 S4
Scramble
Scramble
De-
Document Number: 302875-005
MLT3
MLT3
Revision Date: 27-Oct-2005
pattern: 0, +1, 0, -1, 0, +1...
pattern: 0, +1, 0, -1, 0, +1...
All transitions must follow
All transitions must follow
0
0
No Transition = 0.
No Transition = 0.
Transition = 1.
Transition = 1.
+1
+1
Datasheet
B3467-01
0
0
-1
-1
0
0