MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 467

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

20.9
All interrupt vectors are internally generated. The MCF5272 does not support external interrupt
acknowledge cycles. The System Integration Module prioritizes all interrupt requests and issues the
appropriate vector number in response to an interrupt acknowledge cycle. Refer to the System Integration
chapter for details on the interrupt vectors and their priorities.
When an external peripheral device requires the services of the CPU, it can signal the ColdFire core to take
an interrupt exception. The external peripheral devices use the interrupt request signals (INTx) to signal
an interrupt condition to the MCF5272. The interrupt exception transfers control to a routine that responds
appropriately.
There are a total of six external interrupt inputs, INT[6:1]. Depending on the pin configuration between
three and six of these pins are available. Each interrupt input pin is dedicated to an external peripheral. It
is possible to have multiple external peripherals share an INTx pin but software must then determine which
peripheral caused the interrupt. The interrupt priority level and the signal level of each interrupt pin are
individually programmable.
The MCF5272 continuously samples the external interrupt input signals and synchronizes and debounces
these signals. An interrupt request must be held constant for at least two consecutive CLK periods to be
considered a valid input. MCF5272 latches the interrupt and the interrupt controller responds as
programmed. The interrupt service routine must clear the latch in the ICR registers.
The MCF5272 takes an interrupt exception for a pending interrupt within one instruction boundary after
processing any other pending exception with a higher priority. Thus, the MCF5272 executes at least one
instruction in an interrupt exception handler before recognizing another interrupt request.
20.10 Bus Errors
The system hardware can use the transfer error acknowledge (TEA) signal to abort the current bus cycle
when a fault is detected. A bus error is recognized during a bus cycle when TEA is asserted.
When the MCF5272 recognizes a bus error condition for an access, the access is terminated immediately.
An access that requires more than one transfer aborts without completing the remaining transfers if TEA
is asserted, regardless of whether the access uses burst or non-burst transfers.
Freescale Semiconductor
Interrupt Cycles
All internal interrupts are level sensitive only. External interrupts are
edge-sensitive as programmed in the PITR. Interrupts must remain stable
and held valid for two clock cycles while they are internally synchronized
and latched.
The signal TEA is not intended for use in normal operation since each chip
select can be programmed to automatically terminate a bus cycle at a time
defined by the bits programmed into the wait state field of the Chip Select
Option Register. There is an on chip bus monitor which can be configured
to generate an internal TEA signal.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
Bus Operation
20-19