MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 219

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 11
Ethernet Module
This chapter begins with a feature-set overview, a functional block diagram, and transceiver connection
information for both MII and seven-wire serial interfaces. The chapter concludes with detailed
descriptions of operation and the programming model.
11.1
The MCF5272’s integrated fast Ethernet media access controller (MAC) performs the full set of IEEE
802.3/Ethernet CSMA/CD media access control and channel interface functions. It requires an external
interface adaptor and transceiver function to complete the interface to the media.
11.1.1
The fast Ethernet controller (FEC) incorporates the following features:
11.2
The FEC is implemented using a combination of hardware and microcode.
block diagram of this module.
Freescale Semiconductor
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Full compliance with the IEEE 802.3 standard
Support for three different physical interfaces:
— 100 Mbps 802.3 media independent interface (MII)
— 10 Mbps 802.3 MII
— 10 Mbps seven-wire interface
Half-duplex 100-Mbps operation at system clock frequency Š 50 MHz
448 bytes total on-chip transmit and receive FIFO memory to support a range of bus latencies
Note: the total FIFO size is 448 bytes. It is not intended to hold entire frames but only to
compensate for external bus latency. The FIFO can be partitioned on any 32-bit boundary between
receive and transmit, for example, 32 x 56 receive and 32 x 56 transmit.
Retransmission from transmit FIFO following a collision, no processor bus used
Automatic internal flushing of the receive FIFO for runts and collisions with no processor bus use
Overview
Module Operation
Features
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure 11-1
shows a functional
11-1