MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 386

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

UART Modules
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive
buffer is read. The USRn should be read before reading the receive buffer. If all 24 receiver holding
registers are full, a new character is held in the receiver shift register until space is available. However, if
a second new character is received, the character in the receiver shift register is lost, the FIFO is unaffected,
and USRn[OE] is set when the receiver detects the start bit of the new overrunning character.
Visibility into the status of the FIFO is provided by various bits and interrupts, as shown in
To support flow control, the receiver can be programmed to automatically negate and assert RTS, in which
case the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full.
The receiver asserts RTS when a FIFO position becomes available; therefore, overrun errors can be
prevented by connecting RTS to the CTS input of the transmitting device.
16.5.3
The UART can be configured to operate in various looping modes as shown in
are useful for local and remote system diagnostic functions and are described in the following paragraphs
and in
The UART’s transmitter and receiver should be disabled when switching between modes, as the selected
mode is activated immediately upon mode selection, regardless of whether a character is being received
or transmitted.
16-26
Section 16.3, “Register
USR[FFULL] = 1
USR[RxRDY] = 1
USR[RxFIFO] = 1
USR[RxFTO] = 1
URF[RXS]
URF[RXB]
Status Bit
Looping Modes
The receiver can still read characters in the FIFO stack if the receiver is
disabled. If the receiver is reset, the FIFO stack, RTS control, all receiver
status bits, and interrupt requests are reset. No more characters are received
until the receiver is reenabled.
MCF5272 ColdFire
All FIFO positions contain data
At least one character is available to be read by the CPU.
The programmed level of fullness (UTF[RXS]) has been reached.
The receiver FIFO holds unread data, and the FIFO status
has not changed in at least 64 receiver clocks.
Indicates the level of fullness of the receiver FIFO
Indicates the number of characters, 0–24, in the receiver FIFO.
Descriptions.”
Table 16-17. Receiver FIFO Status Bits
®
Integrated Microprocessor User’s Manual, Rev. 3
Indicated Condition
NOTE
Figure
Freescale Semiconductor
16-26. These modes
Interrupt
Yes
Yes
Yes
Yes
Table
16-17.