MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 115

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Table 4-8
Freescale Semiconductor
30–29
26–25
23–11
Bits
7–6
4–2
31
28
27
24
10
9
8
5
CINVA
DBWE
CENB
Name
CFRZ
describes CACR fields.
CDPI
CEIB
DCM
DWP
—
—
—
—
—
Enable cache.
0 Cache disabled. The cache is not operational, but data and tags are preserved.
1 Cache enabled.
Reserved, should be cleared.
Disable CPUSHL invalidation.
0 Cache disabled
1 Cache enabled
Cache freeze. Allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches
can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given
cache location is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ
is asserted.
0 Normal operation
1 Freeze valid cache lines
Reserved, should be cleared.
Cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Note the caches are not
cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate invalidation of the entire cache. The cache controller sequentially clears V in all sets.
Reserved, should be cleared.
Default noncacheable fill buffer. Determines if the fill buffer can store noncacheable accesses
0 Fill buffer not used to store noncacheable instruction accesses (16 or 32 bits).
1 Fill buffer used to store noncacheable accesses. The fill buffer is used only for normal (TT = 0)
Note that this feature can cause a coherency problem for self-modifying code. If CEIB = 1 and a
cache-inhibited access uses the fill buffer, instructions remain valid in the fill buffer until a
cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a fill.
Default cache mode. See
0 Default cacheable
1 Default noncacheable
Default buffered write enable. Defines the default value for enabling buffered writes. Generally, enabled
buffered writes provide higher system performance but recovery from access errors can be more difficult.
For the ColdFire CPU, reporting access errors on operand writes is always imprecise and enabling
buffered writes simply further decouples the write instruction from the signaling of the fault
0 Termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle
1 A local bus write cycle is terminated immediately and the operation buffered in the bus controller.
Reserved, should be cleared.
Default write protect.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
Subsequent accesses stall until invalidation finishes, at which point, CINVA is automatically cleared.
This operation takes 64 clock cycles.
instruction reads of a noncacheable region. Instructions are loaded into the fill buffer by a burst access
(same as a line fill). They stay in the buffer until they are displaced, so subsequent accesses may not
appear on the external bus.
completes.
Operand write cycles are effectively decoupled between the processor's local bus and the external bus.
MCF5272 ColdFire
Table 4-8. CACR Field Descriptions
®
Section 4.5.2.3, “Caching
Integrated Microprocessor User’s Manual, Rev. 3
Description
Modes.”
Local Memory
4-13