MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 172

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

System Integration Module (SIM)
If an interrupt timeout value is programmed in WIRR, and this value is reached prior to the reset timeout
value, WER[WIE] is set and a maskable interrupt is issued at the level defined by ICR4[SWTOIPL].
The software watchdog consists of a 15-bit counter with a 15-bit prescaler. It counts up to a maximum of
32768, with a resolution of 32768 clock periods. Thus, at 66 MHz, the resolution of the watchdog is 0.5
msec, with a maximum timeout period of 32768 * 32768 = 2
6.2.8.1
The watchdog reset reference register (WRRR),
watchdog timeout causing a reset.
Table 6-9
6.2.8.2
The watchdog interrupt reference register (WIRR),
software watchdog timeout causing an interrupt.
Table 6-10
6-12
15–1
Bits
0
Address
Address
Timeout = (WRRR +1) * 32768 clocks
Field
Reset
Reset
REF
EN
Field
Field
R/W
R/W
describes WRRR fields.
describes WIRR fields.
Watchdog Reset Reference Register (WRRR)
Watchdog Interrupt Reference Register (WIRR)
15
15
Reference value. This field determines the reset timeout value.Reset initializes this register to 0xFFFE,
disabling the watchdog timer and setting it to the maximum timeout value.
Enable watchdog. When enabled, software should periodically write to WCR to avoid reaching the reset
reference value.
0 Watchdog timer disabled.
1 Watchdog timer enabled.
MCF5272 ColdFire
Figure 6-9. Watchdog Interrupt Reference Register (WIRR)
Figure 6-8. Watchdog Reset Reference Register (WRRR)
Table 6-9. WRRR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
1111_1111_1111_1110
1111_1111_1111_1110
Figure
MBAR + 0x280
MBAR + 0x284
Figure
REF
REF
Description
R/W
R/W
6-8, contains the reference value for the software
6-9, contains the reference value for the
30
clock periods or 16.267 S.
Freescale Semiconductor
1
1
IEN
EN
0
0