MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 21

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Paragraph
Number
12.4 Software Architecture and Application Notes ......................................................................... 12-31
12.5 Line Interface ........................................................................................................................... 12-36
13.1 Introduction ................................................................................................................................ 13-1
13.2 GCI/IDL Block .......................................................................................................................... 13-3
13.3 PLIC Timing Generator ........................................................................................................... 13-11
Freescale Semiconductor
12.4.1 USB Module Initialization ........................................................................................... 12-31
12.4.2 USB Configuration and Interface Changes .................................................................. 12-31
12.4.3 FIFO Configuration ...................................................................................................... 12-32
12.4.4 Data Flow ..................................................................................................................... 12-32
12.4.5 Class- and Vendor-Specific Request Operation ............................................................ 12-34
12.4.6 remote wakeup and resume Operation ......................................................................... 12-35
12.4.7 Endpoint Halt Feature ................................................................................................... 12-35
12.5.1 Attachment Detection ................................................................................................... 12-36
12.5.2 PCB Layout Recommendations ................................................................................... 12-36
12.5.3 Recommended USB Protection Circuit ........................................................................ 12-37
13.2.1 GCI/IDL B- and D-Channel Receive Data Registers ..................................................... 13-3
13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers ................................................... 13-4
13.2.3 GCI/IDL B- and D-Channel Bit Alignment ................................................................... 13-5
13.2.4 GCI/IDL Looping Modes ............................................................................................... 13-8
13.2.5 GCI/IDL Interrupts ......................................................................................................... 13-9
12.4.4.1 Control, Bulk, and Interrupt Endpoints .......................................................... 12-33
12.4.4.2 Isochronous Endpoints .................................................................................... 12-33
13.2.3.1 B-Channel Unencoded Data ............................................................................. 13-5
13.2.3.2 B-Channel HDLC Encoded Data ...................................................................... 13-6
13.2.3.3 D-Channel HDLC Encoded Data ..................................................................... 13-6
13.2.3.4 D-Channel Unencoded Data ............................................................................. 13-7
13.2.3.5
13.2.4.1 Automatic Echo Mode ...................................................................................... 13-9
13.2.4.2 Local Loopback Mode ...................................................................................... 13-9
13.2.4.3 Remote Loopback Mode ................................................................................... 13-9
13.2.5.1 GCI/IDL Periodic Frame Interrupt ................................................................... 13-9
13.2.5.2
13.2.5.3 Interrupt Control ............................................................................................. 13-11
12.4.4.1.1 IN Endpoints .......................................................................................... 12-33
12.4.4.1.2 OUT Endpoints ...................................................................................... 12-33
12.4.4.2.1 IN Endpoints .......................................................................................... 12-34
12.4.4.2.2 OUT Endpoints ...................................................................................... 12-34
MCF5272 ColdFire
GCI/IDL D-Channel Contention ..................................................................... 13-8
GCI Aperiodic Status Interrupt ...................................................................... 13-10
Physical Layer Interface Controller (PLIC)
Table of Contents (Continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Chapter 13
Title
Number
Page
xxi