MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 280

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Universal Serial Bus (USB)
12.3.2.15 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0
Figure 12-18
Table 12-14
registers.
12-22
31–17
Bits
16
Reset
Reset
Reset
Reset
Field
Field
Field VEND_REQ FRM_MAT
Field OUT_EOT
Addr
R/W
R/W
R/W
R/W
DEV_CFG
lists field descriptions for the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt
Interrupt Registers (EP0ISR)
shows the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt registers.
Name
31
23
15
7
Interrupt bits are reset by writing a 1 to the specified bits. Writing 0 has no
effect.
—
MCF5272 ColdFire
OUT_EOP
Figure 12-18. USB Endpoint 0 Interrupt Mask (EP0IMR)
Reserved, should be cleared.
Device configuration change interrupt. Set when a device configuration change has been
received. The USB standard device requests SET_CONFIGURATION and SET_INTERFACE
generate a DEV_CFG interrupt. Any IN or OUT packets to the active endpoints cause a NAK
response to the host while this bit is set in order to allow the user to initialize the endpoints’
FIFO’s. Note that if one of these requests is done repeatedly and therefore the registers don’t
change, a DEV_CFG interrupt is still generated. If debug mode is enabled, a change in FAR also
generates an interrupt.
0 No interrupt pending
1 Device configuration change received
14
6
and General/Endpoint 0 Interrupt Registers (EP0ISR)
Table 12-14. EP0IMR and EP0ISR Field Descriptions
MBAR + 0x108C (EP0IMR); MBAR + 0x106C (EP0ISR)
OUT_LVL
ASOF
13
5
®
Integrated Microprocessor User’s Manual, Rev. 3
IN_EOT
SOF
—
12
NOTE
4
0000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R/W
—
WAKE_CHG
IN_EOP
Description
11
3
RESUME
UNHALT
10
2
SUSPEND
HALT
17
9
1
Freescale Semiconductor
DEV_CFG
RESET
IN_LVL
24
16
8
0