DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 70

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
Chapter 5 Resets, Interrupts, and System Configuration
5.7.3
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
70
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
reset:
other
POR
LVR:
Field
ILOP
POR
COP
LOC
LVD
Any
PIN
7
6
5
4
2
1
W
R
U = Unaffected by reset
POR
System Background Debug Force Reset Register (SBDFR)
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Loss-of-Clock Reset — Reset was caused by a loss of external clock.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
U
1
0
7
PIN
(1)
0
0
6
Writing any value to SRS address clears COP watchdog timer.
Table 5-3. SRS Register Field Descriptions
Figure 5-3. System Reset Status (SRS)
MC9S08JM16 Series Data Sheet, Rev. 2
COP
(1)
0
0
5
ILOP
(1)
0
0
4
Description
3
0
0
0
0
LOC
(1)
0
0
2
Freescale Semiconductor
LVD
1
1
0
1
—
0
0
0
0