DEMO9S08JM16 Freescale Semiconductor, DEMO9S08JM16 Datasheet - Page 363

• Manufacturer Part Number: DEMO9S08JM16
• Description: BOARD DEMO FOR JM16 FAMI
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08JM16

• Contents: Board with Daughter card, Cable, Documentation, Mini-AB USB Kit
• Processor To Be Evaluated: MC9S08JM16
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: Flexis - S08JM
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08JM16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Freescale Semiconductor
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
interval.
Jitter measurements are based upon a 48 MHz MCGOUT clock frequency.
Below D
is already in lock, then the MCG may stay in lock.
Below D
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
3
4
5
6
7
2
8
9
lock
unl
C
minimum, the MCG will not exit lock if already in lock. Above D
minimum, the MCG is guaranteed to enter lock. Above D
Control Timing
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time
low output drive (PTxDS = 0),(load = 50 pF)
high output drive (PTxDS = 1), (load = 50 pF)
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
DD
and V
cyc
Parameter
= 1/f
3
3
SS
2
2
and variation in crystal oscillator frequency increase the C
Bus
DD
2
MC9S08JM16 Series Data Sheet, Rev. 2
)
and 80% V
Table A-12. Control Timing
DD
DD
levels. Temperature range –40 °C to 85 °C.
4
= 5.0 V, 25 °C unless otherwise stated.
t
t
t
Symbol
ILIH,
ILIH,
Rise
lock
t
t
t
MSSU
t
t
rstdrv
f
extrst
MSH
LPO
Bus
, t
t
t
maximum, the MCG will not enter lock. But if the MCG
IHIL
IHIL
Fall
unl
maximum, the MCG is guaranteed to exit lock.
1.5 × t
1.5 x t
66 × t
Min
700
100
500
100
100
100
DC
—
—
cyc
cyc
cyc
Appendix A Electrical Characteristics
Typical
Jitter
40
75
11
35
—
—
—
percentage for a given
1
1300
Max
24
—
—
—
—
—
—
Bus
.
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
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