C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 63

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9)
The C8051F360/1/2/6/7/8/9 devices include a 10-bit current-mode Digital-to-Analog Converter (IDAC).
The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA,
1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see
SFR Definition 6.1). When IDA0EN is set to ‘0’, the IDAC port pin (P0.4 for C8051F360, P0.1 for
C8051F361/2/6/7/8/9) behaves as a normal GPIO pin. When IDA0EN is set to ‘1’, the digital output drivers
and weak pullup for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output.
An internal bandgap bias generator is used to generate a reference current for the IDAC whenever it is
enabled. When using the IDAC, the appropriate bit in the P0SKIP register should be set to ‘1’ to force the
Crossbar to skip the IDAC pin.
6.1.
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup-
ports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output
updates on a write to IDA0H, on a Timer overflow, or on an external pin edge.
6.1.1. Update Output On-Demand
In its default mode (IDA0CN.[6:4] = ‘111’) the IDA0 output is updated “on-demand” on a write to the high-
byte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode,
and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the
IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data reg-
isters. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be
IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by
initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 6.2 for
information on the format of the 10-bit IDAC data word within the 16-bit SFR space).
IDA0 Output Scheduling
IDA0OMD1
IDA0OMD0
IDA0CM2
IDA0CM1
IDA0CM0
IDA0EN
Figure 6.1. IDA0 Functional Block Diagram
8
2
10
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
IDA0
IDA0
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