C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 242

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
242
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode.
Bit 1:
Bit 0:
SFR Page:
SFR Address:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic ‘1’ by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) to indicate a write to
the SPI0 data register was attempted while a data transfer was in progress. It must be
cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) when the receive
buffer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Selects between the following NSS operation modes:
(See Section 20.2 and Section 20.3).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
TXBMT: Transmit Buffer Empty.
This bit will be set to logic ‘0’ when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic ‘1’,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
all pages
0xF8
WCOL
assume the value of NSSMD0.
R/W
Bit6
SFR Definition 20.2. SPI0CN: SPI0 Control
MODF
R/W
Bit5
(bit addressable)
RXOVRN NSSMD1 NSSMD0
R/W
Bit4
Rev. 1.0
R/W
Bit3
R/W
Bit2
TXBMT
Bit1
R
SPIEN
R/W
Bit0
00000110
Reset Value