C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 154

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
15.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of five steps:
Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 15.2.
15.3. Port Configuration
The External Memory Interface appears on Ports 1, 2 (non-multiplexed mode only), 3, and 4 when it is
used for off-chip memory access. When the EMIF is used in multiplexed mode, the Crossbar should be
configured to skip over the ALE control line (P0.0) using the P0SKIP register. The other control lines, /RD
(P4.4) and /WR (P4.5), are not available on the Crossbar and do not need to be skipped. For more infor-
mation about configuring the Crossbar, see Section “17.3. General Purpose Port I/O” on page 190. The
EMIF pinout is shown in Table 15.1 on page 155.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “17. Port Input/Out-
put” on page 183 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic ‘1’.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
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1. Configure the Output Modes of the associated port pins as either push-pull or open-drain
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to
3. Select Multiplexed mode or Non-multiplexed mode.
4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
5. Set up timing to interface with off-chip memory or peripherals.
(push-pull is most common), and skip the associated pins in the crossbar.
logic ‘1’).
select, or off-chip only).
Rev. 1.0