C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 27
![KIT DEV FOR C8051F360 FAMILY](/photos/9/23/92333/c8051f360dk_sml.jpg)
C8051F360DK
Manufacturer Part Number
C8051F360DK
Description
KIT DEV FOR C8051F360 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F360DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F36x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1410
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real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
1.7.
The C8051F360/1/2/6/7/8/9 devices include an on-chip 10-bit SAR ADC with up to 21 channels for the dif-
ferential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with
an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both
positive and negative ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Tem-
perature Sensor output and the power supply voltage (V
may shut down the ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal (CNVSTR). This flexibility allows the start of conversion to be triggered by soft-
ware events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indi-
10-Bit Analog to Digital Converter
Capture/Compare
Module 0
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
SYSCLK
External Clock/8
ECI
Capture/Compare
Module 1
CLOCK
MUX
PCA
Figure 1.10. PCA Block Diagram
16-Bit Counter/Timer
Capture/Compare
Module 2
Crossbar
Port I/O
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
DD
Capture/Compare
) are available as ADC inputs. User firmware
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5
27
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