DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 89

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.4.2
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTBSEn). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
Freescale Semiconductor
PTBPE[7:0]
PTBSE[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTBPE7
PTBSE7
Output Slew Rate Control Enable (
Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTBDDn is 0. For port B pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When bit 0, 1, 3, 6, or 7 of port B
is enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable
pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
0
1
7
7
PTBPE6
PTBSE6
Figure 6-16. Slew Rate Control Enable for Port B (PTBSE)
0
1
6
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 6-15. Pullup Enable for Port B (PTBPE)
Table 6-8. PTBPE Field Descriptions
Table 6-9. PTBSE Field Descriptions
PTBPE5
PTBSE5
0
1
5
5
PTBPE4
PTBSE4
0
1
4
4
Description
Description
PTBSE)
PTBPE3
PTBSE3
3
0
3
1
PTBPE2
PTBSE2
0
1
2
2
Chapter 6 Parallel Input/Output
PTBPE1
PTBSE1
0
1
1
1
PTBPE0
PTBSE0
0
1
0
0
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