PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 307

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
R/W-x
R/W-x
EID15
R/W-x
SID2
EID7
This bit is available in Mode 1 and 2 only.
SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18
Unimplemented: Read as ‘0’
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
EXIDEN: Extended Identifier Filter Enable Mask bit
1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0 = Both standard and extended identifier messages will be accepted
Unimplemented: Read as ‘0’
EID17:EID16: Extended Identifier Mask bits
EID15:EID8: Extended Identifier Mask bits
EID7:EID0: Extended Identifier Mask bits
EID14
R/W-x
R/W-x
R/W-x
SID1
EID6
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-x
R/W-x
EID13
R/W-x
SID0
EID5
PIC18F2682/2685/4682/4685
EID12
R/W-x
R/W-x
EID4
U-0
—
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
‘0’ = Bit is cleared
EXIDEN
R/W-0
R/W-x
EID11
R/W-x
EID3
(1)
(1)
R/W-x
EID10
R/W-x
EID2
U-0
—
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
R/W-x
EID17
R/W-x
R/W-x
EID9
EID1
DS39761C-page 307
EID16
R/W-x
R/W-x
R/W-x
EID8
EID0
bit 0
bit 0
bit 0