PCM18XT0 Microchip Technology, PCM18XT0 Datasheet - Page 138

• Manufacturer Part Number: PCM18XT0
• Description: MODULE PROC PIC18F4685
• Manufacturer: Microchip Technology

Specifications of PCM18XT0

• Accessory Type: Processor Module
• Product: Microcontroller Modules
• Core Processor: PIC18F4685
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

PIC18F2682/2685/4682/4685
TABLE 10-5:
DS39761C-page 138
RC0/T1OSO/
T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL RC3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Legend:
Pin Name
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input;
TTL = TTL Buffer Input; I
Function
RC0
T1OSO
T13CKI
RC1
T1OSI
RC2
CCP1
SCK
SCL
RC4
SDI
SDA
RC5
SDO
RC6
TX
CK
RC7
RX
DT
PORTC I/O SUMMARY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
C = Inter-Integrated Circuit; SMBus = System Management Bus
TRIS
0
1
x
1
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
0
1
1
0
1
1
1
1
I
I
2
2
Buffer
C/SMB I
C/SMB I
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATC<0> data output.
PORTC<0> data input.
Timer1 oscillator output – overrides the TRIS<0> control when enabled.
Timer1/Timer3 clock input.
LATC<1> data output.
PORTC<1> data input.
Timer1 oscillator input – overrides the TRIS<1> control when enabled.
LATC<2> data output.
PORTC<2> data input.
CCP1 compare output.
CCP1 capture input.
LATC<3> data output.
PORTC<3> data input.
SPI clock output (MSSP module) – must have TRIS set to ‘1’ to allow the
MSSP module to control the bidirectional communication.
SPI clock input (MSSP module).
I
allow the MSSP module to control the bidirectional communication.
LATC<4> data output.
PORTC<4> data input.
SPI data input (MSSP module).
I
allow the MSSP module to control the bidirectional communication.
the MSSP module to control the bidirectional communication.
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module).
LATC<6> data output.
PORTC<6> data input.
EUSART data output.
EUSART synchronous clock output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
EUSART synchronous clock input.
LATC<7> data output.
PORTC<7> data input.
EUSART asynchronous data input.
EUSART synchronous data output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
EUSART synchronous data input.
2
2
2
2
C™/SMBus clock output (MSSP module) – must have TRIS set to ‘1’ to
C/SMBus clock input.
C/SMBus data output (MSSP module) – must have TRIS set to ‘1’ to
C/SMBus data input (MSSP module) – must have TRIS set to ‘1’ to allow
Description
© 2009 Microchip Technology Inc.