HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 53

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

7) New units, ‘
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
9) Input clock jitter spec parameter. These parameters and the ones in
10) These parameters are specified per their average values, however it is understood that the relationship as defined in
11)
12) DAL = WR + RU{
13)
14) Input waveform timing
15)
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
17) Input waveform timing
18) If
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
20)
21)
22) Input waveform timing is referenced from the input signal crossing at the
23) Input waveform timing is referenced from the input signal crossing at the
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
25)
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
– 272 ps and
t
= - 900 ps – 293 ps = – 1193 ps and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
of
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
of the division is not already an integer, round up to the next highest integer.
Example: For DDR2–533 at
t
the input signal crossing at the
at the
V
t
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
The spec values are not affected by the amount of clock jitter applied (i.e.
crossing. That is, these parameters should be met whether clock jitter is present or not.
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
See
((L/U/R)DQS / DQS) crossing.
t
It is used in conjunction with t
following equation;
minimum of the actual instantaneous clock low time.
t
which specifies when the device output is no longer driving (
to the device under test. See
to the device under test. See
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
t
the max column. {The less half-pulse width distortion present, the larger the
Examples:
1) If the system provides
2) If the system provides
DQSCK.MAX(DERATED)
CKE.MIN
DAL.nCK
DQSQ
HP
HZ
QH
IH.DC.MIN
t
Chapter
DS
is the minimum of the absolute half period of the actual input clock.
and
=
Figure
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
or
t
HP
V
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
t
= WR [nCK] +
IL.DC
t
LZ
DH
. See
–
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
t
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
t
7.3).
QHS
9.
CK.AVG
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
t
CK
t
ERR(6- 10PER).MAX
Figure
, where:
‘ is used for both concepts. Example:
t
RP
t
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
=
IS
t
(ns) /
HP
t
+ 2 x
DQSCK.MAX
t
9.
t
t
= MIN (
nRP.nCK
DS
DH
t
HP
t
t
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
HP
HP
CK
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
t
CK
is the minimum of the absolute half period of the actual input clock; and
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
t
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
CK
QHS
Figure
Figure
= + 293 ps, then
+
= WR + RU{
t
CH.ABS
–
V
t
= 3.75 ns with
IH
IH.DC
t
to derive the DRAM output timing
ERR(6-10PER).MIN
.
,
t
10.
10.
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
LZ.DQ.MAX(DERATED)
t
CL.ABS
t
RP
), where,
[ps] /
t
t
WR
DQSCK.MIN(DERATED)
= 400 ps + 272 ps = + 672 ps. Similarly,
programmed to 4 clocks.
t
CK.AVG
t
t
XP
CH.ABS
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
t
[ps] }, where WR is the value programmed in the EMR.
CK.AVG
t
is the minimum of the actual instantaneous clock high time;
HZ
), or begins driving (
+
53
=
t
t
ERR.2PER(Min)
t
Chapter 7.3
DQSCK.MIN
QH
. The value to be used for
t
HP
V
V
IL.DC
IH.AC
t
is an input parameter but not an input specification parameter.
JIT.PER
t
t
DAL
t
QH
–
CK
level for a rising signal and
level for a rising signal and
.
t
ERR(6-10PER).MAX
value is; and the larger the valid data eye will be.}
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
are referred to as 'input clock jitter spec parameters' and
refers to the application clock period.
,
t
t
CK.AVG
JIT.CC
t
LZ
) .
, etc.), as these are relative to the clock signal
t
t
t
1-Gbit Double-Data-Rate-Two SDRAM
‘ represents the actual
QH
QH
LZ.DQ
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
of 975 ps minimum.
of 1080 ps minimum.
for DDR2–667 derates to
= – 400 ps – 293 ps = – 693 ps and
t
V
QH
IL.AC
t
QHS
t
calculation is determined by the
ERR(6-10per)
level to the differential data strobe
is the specification value under
V
V
IH.DC
IL.AC
V
of the input clock. (output
for a falling signal applied
for a falling signal applied
t
il(DC)MAX
Internet Data Sheet
CK.AVG
Chapter 7.3
t
ERR(6-10PER).MIN
V
IL.DC.MAX
of the input clock
t
LZ.DQ.MIN(DERATED)
and
t
t
t
JIT.PER
CL.ABS
RP
, if the result
V
V
ih(DC)MIN
and
IH.AC
,
is the
between
t
JIT.CC
=
level
.
,