HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 36

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

5.4
This chapter describes the Output Buffer Characteristics.
1)
2) The values of
3)
1) SSTL_18 test load for
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Symbol
I
I
Symbol
V
V
V
OH
OL
OH
OL
OTR
V
plus a noise margin and
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
V
additionally to the 25 Ohm termination resistor into
effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a
minimum requirement of 603 mV swing relative to
DDQ
DDQ
= 1.7 V;
= 1.7 V;
Parameter
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
I
V
V
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
OH(dc)
OUT
OUT
= 1.42 V. (
= 280 mV.
Output Buffer Characteristics
and
V
OH
I
V
OL(dc)
IL.MAX
and
V
are based on the conditions given in
V
V
OUT
minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
OUT
OL
–
is different from the referenced load described. The SSTL_18 test load has a 20 Ohm series resistor
/
V
I
DDQ
OL
must be less than 21 Ohm for values of
) /
I
OH
must be less than 21 Ohm for values of
V
V
Differential DC and AC Input and Output Logic Levels Diagram
TT
TT
, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
. The SSTL_18 definition assumes that
36
1)
and
–13.4
SSTL_18
13.4
3)
. They are used to test drive current capability to ensure
V
OUT
SSTL_18
V
V
0.5 ×
between 0 V and 280 mV.
SSTL_18 Output AC Test Conditions
TT
TT
V
1-Gbit Double-Data-Rate-Two SDRAM
OUT
SSTL_18 Output DC Current Drive
+ 0.603
– 0.603
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
V
between
DDQ
±
335 mV must be developed across the
Unit
mA
mA
V
DDQ
and
Internet Data Sheet
V
DDQ
Unit
V
V
V
TABLE 37
TABLE 38
FIGURE 5
– 280 mV.
Note
1)2)
2)3)
Note
1)
1)
V
IH.MIN
.