HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet
HYB18T1G160BF-5
Specifications of HYB18T1G160BF-5
Related parts for HYB18T1G160BF-5
HYB18T1G160BF-5 Summary of contents
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... All Adapted internet edition Added PG-TFBGA-92 HYB18T1G167BF-3.7, HYB18T1G167BF-3S, HYB18T1G167BF-3, HYB18T1G167BF-2.5, HYB18T1G167BF-25F, HYB18T1G160BFV-3.7, HYB18T1G160BFV-3S Previous Revision: 2007-05, Rev. 1.2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Overview This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 1-Gbit Double-data-Rate SDRAM offers the following key features: ± • 1.8 V 0.1 V Power Supply ± 1.8 ...
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Product Type Speed Code Speed Grade f Max. Clock Frequency @CL5 CK5 f @CL4 CK4 f @CL3 CK3 t Min. RAS-CAS-Delay RCD t Min. Row Precharge Time RP t Min. Row Active Time RAS t Min. Row Cycle Time RC ...
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... HYB18T1G400BF-3S DDR2-667D 5-5-5 ×4 HYB18T1G400BFL-3S ×8 HYB18T1G800BF-3S ×8 HYB18T1G800BFL-3S ×16 HYB18T1G160BF-3S ×16 HYB18T1G160BFL-3S ×16 HYB18T1G160BFV-3S ×16 HYB18T1G167BF-3S Rev. 1.3, 2007-07 03062006-ZNH8-HURV latched at the cross point of differential clocks (CK rising and device, containing CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 17-bit address bus for × ...
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... HYB18T1G160BFL-3.7 ×16 HYB18T1G160BFV-3.7 ×16 HYB18T1G167BF-3.7 ×4 HYB18T1G400BF-5 DDR2-400B 3-3-3 ×4 HYB18T1G400BFL-5 ×8 HYB18T1G800BF-5 ×8 HYB18T1G800BFL-5 ×16 HYB18T1G160BF-5 ×16 HYB18T1G160BFL-5 Industrial Temperature Range (–40 °C - +85 °C) ×4 HYI18T1G400BF-2.5F DDR2-800D 5-5-5 ×8 HYI18T1G800BF-2.5F ×16 HYI18T1G160BF-2.5F ×4 HYI18T1G400BF-2.5 DDR2-800E 6-6-6 ×8 HYI18T1G800BF-2.5 ×16 HYI18T1G160BF-2.5 × ...
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Product Type Org. Speed Standard Temperature Range (0 °C - +70 °C) ×4 HYB18T1G400BC-2.5F DDR2-800D ×8 HYB18T1G800BC-2.5F ×16 HYB18T1G160BC-2.5F ×4 HYB18T1G400BC-2.5 DDR2-800E ×8 HYB18T1G800BC-2.5 ×16 HYB18T1G160BC-2.5 ×4 HYB18T1G400BC-3 DDR2-667C ×8 HYB18T1G800BC-3 ×16 HYB18T1G160BC-3 ×4 HYB18T1G400BC-3S DDR2-667D ×8 HYB18T1G800BC-3S ×16 HYB18T1G160BC-3S ...
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CAS: Column Address Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Chapter 9 Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM of this data sheet 8 Internet Data Sheet ...
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Configuration This chapter contains the chip configuration and addressing. 2.1 Chip Configuration for PG-TFBGA-68 The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 8 and Table 9 Ball# Name Ball Type ...
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Ball# Name Ball Type A10 ...
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Ball# Name Ball Type V J1 PWR DDL V J7 PWR SSDL Not Connected ×4 Organizations A1, A2, A8, A9 E2, F9, H1,F1, R7, H9, W1, W2, W8, W9, R3 Not Connected ×8 Organization A1, A2, A8, A9, ...
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V V Note: and are power and ground for the DLL. DDL SSDL V are isolated on the device. SSQ Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM Ball Configuration for ×4 components, PG-TFBGA-68 (top view connected ...
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Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads and are ...
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Chip Configuration for PG-TFBGA-84 The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 11 and Ball# Name Ball Type Clock Signals ×16 Organization CKE ...
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Ball# Name Ball Type Data Signals ×16 Organization G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 I/O F9 DQ7 I/O C8 DQ8 I/O C2 DQ9 I/O D7 DQ10 ...
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Ball# Name Ball Type Other Balls ×16 Organization K9 ODT I Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not ...
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Rev. 1.3, 2007-07 03062006-ZNH8-HURV Chip Configuration for x16 Components in PG–TFBGA–84 (Top view) 17 Internet Data Sheet HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM FIGURE 3 ...
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Chip Configuration for PG-TFBGA-92 The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 14 and Ball# Name Ball Type Clock Signals ×16 Organization CKE ...
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Ball# Name Ball Type Data Signals ×16 Organization K8 DQ0 I/O K2 DQ1 I/O L7 DQ2 I/O L3 DQ3 I/O L1 DQ4 I/O L9 DQ5 I/O J1 DQ6 I/O J9 DQ7 I/O F8 DQ8 I/O F2 DQ9 I/O G7 DQ10 ...
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Ball# Name Ball Type Not Connected ×16 Organization A1, A2, A8, A9 D2, V3, V7, V8, AA1, AA2, AA8, AA9 Other Balls ×16 Organization N9 ODT I Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital ...
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DDR2 Addressing This chapter describes the 1-Gbit DDR2 addressing. Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’org’ 2) Referred ...
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Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’org’ 2) Referred to as ’colbits’ colbits × org/8 [Bytes] 3) PageSize = 2 ...
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Functional Description This chapter contains the functional description. 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [1] 0 ...
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Field Bits Type Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 B 100 B 101 B 110 B 111 Burst Type [2:0] w Burst ...
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Field Bits Type Description RDQS 11 w Read Data Strobe Output (RDQS, RDQS DQS 10 w Complement Data Strobe (DQS Output OCD [9:7] w Off-Chip Driver Calibration Program Program 000 B ...
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EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 w Bank Address Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA [15:14] w Bank Adress 00 ...
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Field Bits Type Description Partial Self Refresh for 8 banks PASR [2:0] w Address Bus, Partial Array Self Refresh for 8 Banks Note: Only for 1G and 2G components 000 PASR0 Full Array B 001 PASR1 Half Array (BA[2:0]=000, ...
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Input Pin ×4 Components DQ[3:0] DQS DQS DM ×8 Components DQ[7:0] DQS DQS RDQS RDQS DM ×16 Components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM Note don’t care bit set to low bit ...
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Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
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Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM. Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single ...
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Current State CKE 6) Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other H than listed above 1) Current state is the state of the DDR2 SDRAM ...
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Electrical Characteristics This chapter describes the electrical characteristics. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in 5.1.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ...
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DC Characteristics Input and output 0s are higher with dual-die components compared to standard single-die components, due to the double loading of the input / output pins, except CS[1:0], CKE[1:0] and ODT[1:0] and the additional package internal wiring. Symbol ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac) AC differential cross point output voltage 0.5 × V OX(ac ...
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Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...
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Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT V ± V ± 1 1.8 V 0.1 V DDQ ...
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Input / Output Capacitance This chapter contains the input / output capacitance. Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all ...
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Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS CDIO ...
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Overshoot and Undershoot Specification This chapter contains overshoot and undershoot specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot ...
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AC Overshoot / Undershoot Spec. for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...
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Currents Measurement Conditions This chapter describes the current measurement specifications and conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) Address ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...
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Symbol 25F 2.5 DDR2 - 800 DDR2 - 800 DDR2 - 667 DDR2 - 667 DDR2 - 533 DDR2 - 400 Max. Max. I 125 125 DD0 150 150 I 135 135 DD1 160 160 DD2P I ...
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Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications ( Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock ...
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
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V 3) Inputs are not recognized as valid until 4) The output timing reference voltage level calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to ...
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Component AC Timing Parameters List of Timing Parameters Tables. Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low ...
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Parameter DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (8 banks) command period Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB ...
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These parameters are specified per their average values, however it is understood that the relationship as defined in the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be ...
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t t ...
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Parameter Control & address input pulse width for each input Address and control input setup time DQ low impedance time from CK/CK DQS/DQS low-impedance time from MRS command to ODT update delay Mode register set command cycle ...
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New units, ‘ ‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘ CK.AVG under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and t ...
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QHS 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual and 2) The worst case push-out of DQS on one transition followed by the worst case pull- ...
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Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM Differential input waveform timing - Differential input waveform timing - 55 Internet Data Sheet FIGURE and DS DS FIGURE and lS lH ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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Parameter Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B ...
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MIN ( , ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can greater than the minimum specification ...
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Parameter DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Four Activate Window period Four Activate Window period Clock half period ...
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Parameter Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge V = 1.8 V ± 0 ...
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Jitter Definition and Clock Jitter Specification Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table provides an overview of the terminology. Symbol Parameter t Average clock ...
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Symbol Parameter t Cumulative error ERR.nPER across n cycles t Average high-pulse CH.AVG width t Average low-pulse CL.AVG width t Duty-cycle jitter JIT.DUTY The following parameters are specified per their average values however understood that the following relationship ...
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Symbol Parameter Min Clock period CK.ABS t t Clock high-pulse width CH.ABS t t Clock low-pulse width CL.ABS Example: for DDR2-667, tCH.ABS(Min) = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps. Table ...
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ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down ...
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Package Dimensions This chapter describes the package dimensions. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM Package Outline P(G)-TFBGA-68 65 Internet Data Sheet ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM Package Outline P(G)-TFBGA-84 66 Internet Data Sheet FIGURE 12 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-92 67 Internet Data Sheet FIGURE 13 ...
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... Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR2 SDRAM HYB 18 DDR2 SDRAM HYB 18 Field Description 1 Qimonda Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5+6 Number of I/Os 7 Product Variations ...
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Field Description 11 Speed Grade Rev. 1.3, 2007-07 03062006-ZNH8-HURV Values Coding –1.9 DDR2–1066 –25F DDR2–800 5–5–5 –2.5 DDR2–800 6–6–6 –3 DDR2–667 4–4–4 –3S DDR2–667 5–5–5 –3.7 DDR2–533 4–4–4 –5 DDR2–400 3–3–3 69 Internet Data Sheet HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM ...
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List of Figures Ball Configuration for ×4 components, PG-TFBGA-68 (top view ...
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List of Tables Table 1 Performance Tables for –2.5( ...
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... Table 60 ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . 64 Table 61 ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . 64 Table 62 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 63 DDR2 Memory Components Rev. 1.3, 2007-07 03062006-ZNH8-HURV HY[B/I]18T1G[40/80/16]0B[C/F](L/V) 1-Gbit Double-Data-Rate-Two SDRAM 72 Internet Data Sheet ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...