HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 30

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

4
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two
SDRAM.
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register.
6) V
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Function
(Extended) Mode
Register Set
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto-
Precharge
Read
Read with Auto-
Precharge
No Operation
Device Deselect
Power Down Entry
Power Down Exit
and then restarted through the specified initialization sequence before normal operation can continue.
requirements.
REF
must be maintained during Self Refresh operation.
Truth Tables
H
H
L
CKE
Previous
Cycle
H
H
H
L
H
H
H
H
H
H
H
H
Current
Cycle
H
H
L
H
H
H
H
H
H
H
H
X
X
L
H
CS RAS
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
X
H
L
L
L
H
H
H
H
H
X
X
H
X
H
30
CAS WE BA0
L
L
L
X
H
H
H
H
L
L
L
L
H
X
X
H
X
H
L
H
H
X
H
L
L
H
L
L
H
H
H
X
X
H
X
H
BA1
BA2
BA
X
X
X
BA
X
BA
BA
BA
BA
BA
X
X
X
X
1-Gbit Double-Data-Rate-Two SDRAM
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
A[13:11]
OP Code
X
X
X
X
X
Row Address
Column
Column
Column
Column
X
X
X
X
A10 A[9:0]
H
X
X
X
X
X
L
L
H
L
H
X
X
Command Truth Table
X
X
X
X
X
Column
Column
Column
Column
X
X
X
X
Internet Data Sheet
TABLE 25
Note
4)5)
4)
4)6)
4)6)7)
4)5)
4)
4)5)
4)5)8)
4)5)8)
4)5)8)
4)5)8)
4)
4)
4)9)
4)9)
1)2)3)