HYB18T1G160BF-5 Qimonda, HYB18T1G160BF-5 Datasheet - Page 52

• Manufacturer Part Number: HYB18T1G160BF-5
• Description: IC DDR2 SDRAM 1GBIT 84TFBGA
• Manufacturer: Qimonda

Specifications of HYB18T1G160BF-5

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 84-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1018-2

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
Rev. 1.3, 2007-07
03062006-ZNH8-HURV
Parameter
Control & address input pulse width for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
V
REF
V
stabilizes. During the period before
TT
.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
REFI
RFC
RP
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
52
DDR2–667
0.6
200
2 x
t
0
2
0
t
—
—
—
127.5
t
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
Min.
AC.MIN
HP
RP
RFC
–
+ 1 ×
t
AC.MIN
+10
t
QHS
V
REF
t
CK
stabilizes, CKE = 0.2 x
1-Gbit Double-Data-Rate-Two SDRAM
—
—
12
—
12
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
Max.
t
t
—
340
7.8
3.9
—
—
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
AC.MAX
AC.MAX
V
Unit
t
ps
ps
ps
ns
nCK
ns
ps
ps
µs
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
DDQ
Internet Data Sheet
is recognized as low.
Note
23)24)
8)21)
8)21)
34)
34)
25)
26)
27)28)
28)29)
30)
31)32)
31)33)
34)
34)
34)
34)
34)35)
34)
1)2)3)4)5)6)7)