MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 95

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

1
3.7.14
Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals).
Typically a port uses five signals.
The interface is designed to be used with synchronous SIM cards, meaning the SIM module provides the
clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the
SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard
UART data exchanges. All six signals (five for bidirectional Tx/Rx) of the SIM module are asynchronous
with each other.
There are no required timing relationships between signals in normal mode. The SIM card is initiated by
the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no
defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed
information see ISO/IEC 7816).
Freescale Semiconductor
CL of PWMO = 30 pF
Ref No.
2a
2b
3a
3b
4a
4b
1
Subscriber Identity Module (SIM) Timing
PWM Source Clock
System CLK frequency
PWM Output
i.MX25 Applications Processor for Automotive Products, Rev. 9
Output setup time
Output delay time
Clock high time
Clock rise time
Clock low time
Clock fall time
Parameter
Table 73. PWM Output Timing Parameter
Figure 67. PWM Timing
1
4a
2a
2b
Minimum
12.29
9.91
8.71
—
—
—
0
3a
1
Maximum
ipg_clk
9.37
0.5
0.5
3b
—
—
—
4b
MHz
Unit
ns
ns
ns
ns
ns
ns
95