MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 86

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

3.7.9.1.5
The transmitter functions correctly up to an FEC_TX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
FEC_TX_CLK frequency.
Figure 56
in the figure.
1
3.7.9.1.6
Figure 57
the figure.
86
M5
M6
M7
M8
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
ID
FEC_TXD[3:0] (outputs)
FEC_TX_CLK (input)
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
shows MII asynchronous input timings.
shows MII transmit signal timings.
FEC_CRS, FEC_COL
FEC_TX_EN
FEC_TX_ER
MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK)
MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
i.MX25 Applications Processor for Automotive Products, Rev. 9
Figure 56. MII Transmit Signal Timing Diagram
Figure 57. MII Async Inputs Timing Diagram
Characteristic
Table 63. MII Transmit Signal Timing
1
Table 63
M5
Table 64
M6
M7
describes the timing parameters (M5–M8) shown
describes the timing parameter (M9) shown in
M9
Min.
35%
35%
—
M8
5
Max.
65%
65%
—
20
Freescale Semiconductor
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns